The use of a polysilicon layer for local interconnect has been reported in the literature for both bipolar and metal oxide semiconductor (MOS) technologies. In bipolar processes, a polysilicon layer can be used to electrically contact the base and collector and as a diffusion source to form the emitter regions of bipolar transistors. In MOS technologies, a polysilicon layer can be used to electrically contact the source-drain regions of the MOS transistors and form the gates of MOS transistors. Global interconnects can be formed by contacting the polysilicon layer using conventional metal interconnects.
Lateral pnp transistors made with standard processes frequently have an N+polysilicon layer in contact with the N- epitaxial base of the transistor. The N type dopant contained in the N+ polysilicon layer diffuses into the N- epitaxial base altering the properties of the base. As a result, junction breakdown voltages of the transistor occur at approximately six volts.
In programmable array logic circuits, high voltages are applied to the programming pins during programming of the circuits. This programming event requires transistor breakdown voltages in excess of twelve volts for transistor-transistor logic circuits (TTL) and in excess of nine volts for emitter coupled logic (ECL) circuits. For this reason, lateral pnp transistors fabricated with polysilicon layers using the conventional processes and having breakdown voltages of the order of six volts are not suitable for use in programmable array logic circuits.
Fabricating the lateral pnp transistor with undoped, or intrinsic, polysilicide material would prevent the diffusion problem and improve breakdown voltages. Such a transistor, however, has poor current gain characteristics and therefore lacks the speed advantages obtainable from devices using doped polysilicon materials.